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| Data Sheet No. PD60225 IRMCK203 High Performance Sensorless Motion Control IC Features ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! Complete Sensorless control IC for Permanent Magnet AC motors No voltage feedback sensing required Sinusoidal current waveform with Synchronously Rotating Frame closed loop current control High starting torque and smooth speed ramping Direct interface to IR2175 current sensing high voltage IC Auto Retry at startup with presettable torque Versatile loss minimization Space Vector PWM Configurable architecture Serial communication interface (RS232C, RS422, SPI) 2 I C serial interface to 1k bit serial EEPROM for parameter storage for stand alone operation Phase loss/Overcurrent/Overvoltage protection 7-bit discrete I/O for sequencing and status monitor Integrated brake IGBT control ServoDesigner TM Product Summary Max Clock input Sensorless control computation time Speed operating range (typical) 100% Speed control resolution Adjustable current limit at start-up Programmable retry on start-up trials max 16 33.3 MHz 11 usec max < 5% to 15 bit full range Over current, speed, phase loss, dc bus fault protection PWM carrier frequency IR2175 Current feedback data resolution Optional low side 3-leg current sensing Max R3232C speed Optional RS422 communication Package: QFP80 56 Kbps 1 Mbps 16 bit/33MHz 10bit tool for easy operation Parallel interface for microcontroller expansion Description IRMCK203 is a high performance digital motion control IC for Sensorless AC permanent magnet motor application. Control is based on closed loop vector control with sinusoidal Back EMF. With IRMCK203, the users can readily build a high performance Sensorless drive system without any programming effort and minimum start-up time. Built-in unique start-up and ramping algorithm enables wide application. This IC is versatile enough that the users can configure and optimize system performance according to the needs of each application. With International Rectifier iMOTION product including high voltage ICs such as IR2175 current sensing IC and IRAM series of Intelligent IGBT module in combination with IRMCK203, the end result is a fully optimized system with reduced electronics component counts. This simplifies the design for low cost Sensorless drive modules. IRMCK203 can be easily adapted to various permanent magnet motors through ServoDesignerTM tool, which is the fully configurable graphic user interface tool. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. IRMCK203 Overview IRMCK203 is a new International Rectifier integrated circuit device designed for one-chip solution for complete closed loop current control and velocity control for a high performance servo drive system. Unlike a traditional microcontroller or DSP, IRMCK203 does not require any programming to complete complex AC servo algorithm development. Combined with International Rectifier's high voltage gate drive and current sensing IC, the user can implement a complete AC servo control with minimum component count and virtually no design effort. Although IRMCK203 contains dedicated logic to perform closed loop control of AC current and velocity, it has wide range of application coverage through flexible configuration ability. The drive can be easily configured induction machine closed loop vector control or permanent magnet motor servo drive. Rich motion peripherals, analog and digital I/O can also be configured. Host communication logic contains Asynchronous Communication Interface for RS232C or RS422 or RS485 communication interface, a fast slave SPI interface and an 8 bit wide Host Parallel Interface. All communication ports have same access capability to the host register set. The user can write to, and read from the predefined registers to configure and monitor the drive through these communication ports. IRMCK203 Main functions IRMCK203 contains the following functions for AC servo motor control applications: * * * * * * * * * * * * * * * * * * Complete closed loop current control based on Synchronously Rotating Frame Field Orientation. Configurable update rate with PWM carrier frequency. Configurable parameters (all PI controller gains, PI output limit range, current feedback scaling, encoder feedback scaling) Built-in sensorless logic for start-up, ramping, and running conditions Closed loop velocity control based on estimated speed Selectable reference input for torque and speed input Auto Retry (programmable) with presettable torque Analog reference input RS232C/RS422 reference input Dynamic braking control for excess DC bus voltage Cycle-by-cycle on/off Control for Brake IGBT DC bus voltage feedback Loss minimization Space Vector PWM with deadtime insertion IR2175 current sensing IC interface Phase loss, overcurrent (GATEKILL input), overvoltage, undervoltage protection Low cost serial 12bit A/D interface with multiplexer and sample/hold circuit Optional 3-leg current sensing in lieu of IR2175 IC. 4 channel analog output by PWM 0-5 V output, 16kHz cut-off frequency with 2-pole butter-worth filter One channel analog output for Resolver reference (10kHz sinusoidal) Local EEPROM for startup initialization of internal data/parameters through host register interface AT24C01A, 128X8 Versatile host communication interface RS232C or RS422 host interface Fast SPI slave host interface with multi-drop capability Parallel Host interface (total 12 pins) Multiplexed data/address bus * * * This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 2 IRMCK203 Address Enable RD/WR Discrete I/O Start/Stop (Input) E-Stop (Input) FWD/REV (Input) Fault Clear (Input) Fault (Output) SYNC (Output) PWM Enable (Output) LED Two bit bi-color * * This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 3 IRMCK203 Overview........................................................................................................................................................................... 2 IRMCK203 Main functions .............................................................................................................................................. 2 IRMCK203 Block Diagrams............................................................................................................................................. 8 Basic Block Diagram .................................................................................................................................................... 8 Detailed Block Diagram................................................................................................................................................ 9 Input/Output of IRMCK203........................................................................................................................................ 10 Communication Group............................................................................................................................................ 11 Motion Peripheral Group ........................................................................................................................................ 11 Analog interface Group........................................................................................................................................... 11 Discrete I/O Group.................................................................................................................................................. 12 Parallel Interface Group .......................................................................................................................................... 12 CLOCK/PLL management Group .......................................................................................................................... 12 Miscellaneous Group .............................................................................................................................................. 12 Application Connections............................................................................................................................................. 13 IC Crystal Clock Circuitry .......................................................................................................................................... 14 PLL Clock Circuitry.................................................................................................................................................... 15 Low Pass Filter............................................................................................................................................................ 15 Implementing the Low Pass Filter Shield ............................................................................................................... 16 Cp Rp and Cs Component Values........................................................................................................................... 16 PLL Reset.................................................................................................................................................................... 16 DC Electrical Characteristics and Operating Conditions ................................................................................................ 17 Absolute Maximum Ratings........................................................................................................................................ 17 Recommended Operating Conditions ......................................................................................................................... 17 DC Characteristics ...................................................................................................................................................... 18 Common Quiescent and Leakage Current .................................................................................................................. 18 Input Characteristics - Non Schmitt Inputs ................................................................................................................ 18 Input Characteristics - Schmitt Inputs ........................................................................................................................ 18 Output Characteristics................................................................................................................................................. 18 Pin and I/O Characteristic Table ................................................................................................................................. 19 AC Electrical Characteristics and Operating Conditions ................................................................................................ 22 System Level AC Characteristics................................................................................................................................ 22 Sync Pulse to Sync Pulse Timing............................................................................................................................ 22 FAULT and REDLED Response to GATEKILL ................................................................................................... 23 Host Interface AC Characteristics............................................................................................................................... 24 SPI Timing .............................................................................................................................................................. 24 Host Parallel Timing ................................................................................................................................................... 25 Host Parallel Read Cycle......................................................................................................................................... 25 Host Parallel Write Cycle........................................................................................................................................ 26 Discrete I/O Electrical Characteristics ........................................................................................................................ 27 Motion Peripheral Electrical Characteristics............................................................................................................... 28 PWM Electrical Characteristics .............................................................................................................................. 28 IR2175 Interface ..................................................................................................................................................... 28 Analog Interface Electrical Characteristics................................................................................................................. 29 ADC Timing............................................................................................................................................................ 29 PLL Interface Electrical Characteristics...................................................................................................................... 31 Appendix A Host Register Map .................................................................................................................................. 32 Register Access ........................................................................................................................................................... 32 SPI Register Access ................................................................................................................................................ 32 RS-232 Register Access.......................................................................................................................................... 32 Write Register Definitions .......................................................................................................................................... 36 PwmConfig Register Group (Write Registers) ....................................................................................................... 36 CurrentFeedbackConfig Register Group (Write Registers) .................................................................................... 37 SystemControl Register Group (Write Registers)................................................................................................... 38 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 4 IRMCK203 TorqueLoopConfig Register Group (Write Registers)............................................................................................ 38 VelocityControl Register Group (Write Registers)................................................................................................. 39 FaultControl Register Group (Write Registers) ...................................................................................................... 41 SystemConfig Register Group (Write Registers).................................................................................................... 41 EepromControl Registers (Write Registers)............................................................................................................ 42 ClosedLoopAngleEstimator Registers (Write Registers)........................................................................................ 43 OpenLoopAngleEstimator Registers (Write Registers) .......................................................................................... 44 StartupAngleEstimator Registers (Write Registers)................................................................................................ 45 TraceBufferControl Register Group (Write Registers) ........................................................................................... 46 StartupRetrail Registers (Write Registers) .............................................................................................................. 48 Read Register Definitions ........................................................................................................................................... 49 SystemStatus Register Group (Read Registers) ...................................................................................................... 49 DcBusVoltage Register Group (Read Registers) .................................................................................................... 49 FocDiagnosticData Register Group (Read Registers)............................................................................................. 50 FaultStatus Register Group (Read Registers).......................................................................................................... 51 VelocityStatus Register Group (Read Registers) .................................................................................................... 52 CurrentFeedbackOffset Register Group (Read Registers) ...................................................................................... 52 EepromStatus Registers (Read Registers)............................................................................................................... 53 FOCDiagnosticDataSupplement Register Group (Read Registers) ........................................................................ 54 TraceBufferStatus Register Group (Read Registers) .............................................................................................. 54 ProductIdentification Registers (Read Registers) ................................................................................................... 55 Appendix B Package ................................................................................................................................................... 57 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 5 IRMCK203 Figure 1. IRMCS2031 Simplified Blocks ..................................................................................................................... 8 Figure 2: Detailed Block Diagram of IRMCK203............................................................................................................ 9 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 6 IRMCK203 Table 1: Common Values for the Clock Circuit.............................................................................................................. 14 Table 2: PLL Test Pin Assignments................................................................................................................................ 15 Table 3: Absolute Maximum Ratings ............................................................................................................................. 17 Table 4: Recommended Operating Conditions ............................................................................................................... 17 Table 5: DC Characteristics ............................................................................................................................................ 18 Table 6: Non Schmitt Input Characteristics .................................................................................................................... 18 Table 7: Schmitt Input Characteristics ............................................................................................................................ 18 Table 8: Output Characteristics....................................................................................................................................... 18 Table 9: Pin and I/O Characteristics ............................................................................................................................... 21 Table 10: System Level SYNC to SYNC Timing........................................................................................................... 22 Table 11: FAULT and REDLED Response to GATEKILL ........................................................................................... 23 Table 12: SPI Timing ...................................................................................................................................................... 24 Table 13: Host Parallel Read Cycle Timing.................................................................................................................... 25 Table 14: Host Parallel Write Cycle Timing................................................................................................................... 26 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 7 IRMCK203 IRMCK203 Block Diagrams Basic Block Diagram Error! Reference source not found. shows the basic block diagram of the IRMCK203 surrounded by International Rectifiers' ICs. Host communications are provided over SPI, RS-232C or Host parallel ports. Two current sensing ICs (IR2175) and a three phase high voltage gate drive typically implement the high voltage / current interface between the IRMCK203 IC and motor. The IRMCK203 can operate in a "stand-alone" mode without the host controller. utilized to load motor-specific parameters into the IC. A serial EEPROM would be AC Power Analog Monitor EEPROM IRMCS2031 IRMCK203 select Analog Speed Reference 4 channel D/A RS232C or RS422 RAMP Host Register Interface A/D interface DC bus dynamic brake control BRAKE A/D MUX DC bus feedback + - + + - e Rotor Angle/ speed Estimator j Space Vector PWM Dead time IR2136 Host Controller SPI Interface FAULT Plug-N-DriveTM IGBT module IRAMY20UP60A Parallel Interface Configuration Registers Monitoring Registers e j 2/3 Period/Duty counters Period/Duty counters IR2175 IR2175 Motor Figure 1. IRMCS2031 Simplified Blocks Configurable parameters are provided to tailor design to various applications (motor and load). These configurable parameters can be modified via the host register interface through the communication interface. In the IRMCK203 product, a design spread sheet is provided to aid the user for ease of drive start-up, the spread sheet will input high level application data such as motor name plate information, max speed, current limit, speed and current regulator bandwidth, base on this information the program will generate the required configurable parameters. Detail on Drive commissioning is described in the IRMCS2031 Application Development Guide. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 8 IRMCK203 Detailed Block Diagram Figure 2: Detailed Block Diagram of IRMCK203 shows the detailed block diagram or the IRMCK203. All logic and algorithms are pre-programmed, and the user does not need to make any effort to develop code, alleviating the tedious design process. If needed, the user can configure the drive to tailor the control per specific needs to meet the required specification. This configuration can be easily done by accessing the host register interface through the communication interface. Closed Loop Velocity Control, Sequencing Control Update Rate = PWM carrier frequency / 2 EXT_REF I1 x I2 O I1 I3 I3 I2 REF scale 4096 Closed Loop Current Control Update Rate = PWM carrier frequency x1 or x 2 DCV_FDBK Feedforward path enable 2 MUX 8 channel Serial A/D Interface +/-16383 = +/-max_speed INT_VQ SPDKI SPDKP INT_REF Reference Select Velocity Control Enable IQREF VQLIM - VQLIM CURKI CURKP ADS7818 A/D interface DC bus dynamic brake control CNVST CLK DATA 2 Optional Current Sense BRAKE GSenseL GSenseU ModScl + RAMP START STOP DIR FLTCLR SYNC FAULT PWM ACTIVE RCV SND RTS CTS + - PI + IQLIMIDREF PI + VQ Sequence Control + - Accel Rate Decel Rate PI INT_VD - VDLIM Slip gain VDLIM 4096 VD e + j VQS 6 VDS Space Vector PWM Dea d time Gate Signals FAULT IQLIM+ VD enable Slip gain enable PWMmode 2Pen Dtime PWMen AngleScale MaxEncCount SpdScale InitZval 3 Encoder A/B/Z Encoder Hall A/B/C RS232C/ RS422 Interface Configuration Registers Host Register Interface I2 I1 I1 x I2 I3 I3 O dt 0 + Quadrature Decoding 3 EncType InitZ Optional CurrentSense Zpol SCK SDO SDI CS SPI Slave Interface IQ scale 4096 IQ Data Address Control I2 O 17 Parallel Interface Monitoring Registers I1 x I2 I3 I3 I1 ID O I2 I1 x I2 I1 I3 I3 4096 e j IV 2/3 IR2175 interface IR2175 interface Current Offset W Current Offset V Motor Phase Current V Motor Phase Current W IW ID scale +/-16383 = +/-4X of rated current for IQ INT_DAC1 INT_DAC2 INT_DAC3 INT_DAC4 DAC_PWM1 Communication Modules 4ch DAC module DAC_PWM2 DAC_PWM3 DAC_PWM4 +/-4095 = +/-rated ID for IM field flux Figure 2: Detailed Block Diagram of IRMCK203 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 9 IRMCK203 Input/Output of IRMCK203 The I/O signals are shown in Fig. 3. The interface signals are divided into sub-groups. All I/O pins are 3.3V logic interface. For detailed pin assignment, please refer to appendix (Pin definition). Crystal OSC1CLK OSC2CLK BYPASSMODE PLLTEST XPD CHGO AVDD LPVSS VSSHC PLL Clock Control PWMUH PWMUL PWMVH PWMVL PWMWH PWMWL BRAKE FLTCLROUT GATEKILL PWM gate signal Interface SPI Interface RS232C Interface SCLK MISO MOSI CS SND RCV BAUDSEL IFB[0-1] IR2175 Interface D/A Interface (PWM output) DAC[0-3] IRMCK203 ADCLK ADOUT ADCONVST ADMUX[0-2] RESSAMPLE HPD[0-7] A/D Interface Parallel Interface HPOEN HPWEN HPCSN HPA STARTSTOP ESTOP PWMEN FLTCLR SYNC FAULT DIR Discrete I/O RESETN System Reset Serial EEPROM LED/Status SCA SCL REDLED GREENLED Figure 3 Input/Output of IRMCK203 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 10 IRMCK203 Communication Group SPI Interface # SCLK # MISO # MOSI # CS - Input, SPI clock - Output, Master Input and Slave Output, Data output from IRMCK203 - Input, Master Output and Slave Input, Data input from the host - Input, Chip Select I2C Interface for EEPROM # SCA - Bi-directional data, Serial EEROM interface # SCL - Clock, Serial EEROM interface Asynchronous Communication (RS232C, RS422, RS485) Interface # SND - Output, Send data from IRMCK203 # RCV - Input, Receive data to IRMCK203 # BAUDSEL - Baud rate select (57.6k/1M) Motion Peripheral Group PWM # # # # # # # PWMUH PWMUL PWMVH PWMVL PWMWH PWMWL BRAKE - Output, PWM phase U high side gate signal - Output, PWM phase U low side gate signal - Output, PWM phase V high side gate signal - Output, PWM phase V low side gate signal - Output, PWM phase W high side gate signal - Output, PWM phase W low side gate signal - Output, Brake IGBT gate signal IR2175 # IFB0 # IFB1 Fault # # - Input, IR2175 channel 0 input (Phase V) - Input, IR2175 channel 1 input (Phase W) GATEKILL FLTCLROUT - Input, upon assertion, this negates all six PWM signals - Output, Fault clear output Analog interface Group # # # # # # # ADCLK ADOUT ADCONVST ADMUX0 ADMUX1 RESSAMPLE DAC[0-3] - Output, clock signal to ADS7818 Channel 0 A/D converter - Input, serial data from ADS7818 Channel 0 A/D converter - Output, conversion start to ADS7818 Channel 0 A/D converter - Output, multiplexer steering address - Output, multiplexer, steering address - Output, sample/hold control signal channel 0 A/D converter - Output, 4 channel Analog Output (PWM output) This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 11 IRMCK203 Discrete I/O Group # # # # # # START ESTOP FAULTCLR PWMEN SYNC FAULT - Input, Start/Stop command, level sensitive - Input, Stop, state sensitive - Input, Fault clear, edge sensitive - Output, PWM enable/disable state output - Output, SYNC pulse output - Output, Fault state output Parallel Interface Group # # # # # HPD[0-7] HPOEN HPWEN HPCSN HPA - Input/Output, 8bit data/address multiplexed bus for parallel port interface - Input, Output enable strobe for read access - Input, Write enable strobe for write access - Input, Chip Select strobe - Input, Address enable CLOCK/PLL management Group # # # # # # # # # # BYPASSMODE CHGO OSC1CLK OSC2CLK PLLTEST XPD VSSHC MVDD AVDD LPVSS - Input, must be tied to ground - Output, connected to RC filter circuit - Input, connected to Crystal - Output, connected to Crystal - Input must be tied to ground - PLL reset, must be asserted while RESETN is active - Power, must be tied to ground - Power, must be tied to VDD (3.3V) - Power, must be tied to VDD (3.3V) - Power, must be tied to ground Miscellaneous Group # # REDLED GREENLED - Output, LED0 drive signal - Output, LED1 drive signal These SPI interface signals are configured for Slave mode. Therefore the host SPI interface determines SPI clock speed. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 12 IRMCK203 Application Connections Typical application connection is shown in Figure . In order to complete a Sensorless drive control, all necessary components are shown in connection to IRMCK203. Although this is a typical hardware configuration, users can customize the design without changing code by restless programming effort. System Clock 33MHz Crystal OSC1CLK OSC2CLK SCLK MISO PWMUH PWMUL PWMVH PWMVL PWMWH PWMWL BRAKE SND SPI Interface MOSI CS Gate Drive & IGBTs To PC MAX232A RCV GATEKILL FAULTCLR BAUDSEL HPD[0-7] LON3 5V IFB0 Isolator 5V START IFB1 PO Motor Phase Shunt Optional microcontroller 8051 uP HPOEN,HPWEN HPCSN,HPA IR2175 IR2175 Motor Phase Shunt PO Motor Current Sensing Input Switches ESTOP FLTCLR PWMEN FAULT SYNC AD0-CLK AD0-DAT SCA AD0-CNV Isolator IRMCK203 ADS7818 4051 Anaog refernce input DC bus voltage LED Serial EEPROM Bi-Color LED AT24C01A SCL REDLED GREENLED ADMUX0 ADMUX1 ADMUX2 RESSAMPLE DAC0 DAC1 DAC2 DAC3 SCA_ROM SDA_ROM 3-leg shunt current sensing (optional) Analog Output EEPROM (AT24C01) 1kbit User Parameter EEPROM Figure 4. Application Connection of IRMCK203 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 13 IRMCK203 IC Crystal Clock Circuitry The clock input to the IC is a 33.33 MHz crystal oscillator. required to terminate the crystal to the IC. Two shunt capacitors and a possibly a series resistor is The values of the R/C will vary based on actual PCB attributes, and some empirical analysis may be required to get the PLL to start oscillating. Once oscillating, verify that the signal waveform at the OSC1CLK and OSC2CLK pins are sinusoidal rather than trapezoidal. Refer to Table 1: Common Values for the Clock Circuit for suggested R/C values. Most low-cost crystals can be used in this application. An example is a Citizen Part number CM309B33.333MABJT available from Digi-Key under part number 300-4160-1-ND. OSC1CLK IRMCK201 C1 XTAL R2 OSC2CLK R1 C2 Figure 5: Oscillator Circuit COMPONENT XTAL C1 C2 R1 R2 VALUE 33.33 5 5 0 3.9K UNITS MHz pf pf OHM OHM Table 1: Common Values for the Clock Circuit This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 14 IRMCK203 PLL Clock Circuitry The IRACK201 contains a PLL that creates a 2X and 4X clock from the input 33.33 MHz input clock pin. There are a number of pins on the IC allocated for factory testing purposes, and need to be left unconnected. Table 2: PLL Test Pin Assignments shows required PCB signal connections for these pins. PIN NUMBER 1 2 7 15 16 17 18 23 24 25 41 45 56 89 PCB CONNECTION VSS VSS VSS N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C Table 2: PLL Test Pin Assignments Low Pass Filter The low pass filter for this PLL resides between the CHGO and LPVSS pins. Three passive components are required to implement this filter: Cp, Rp and Cs. Figure 6: PLL Low Pass Filter Shielding shows how to place these components around the IC. A shield should be placed below Rp, Cp and Cs made out of copper etch. Shielded by LPVSS CHGO Rp IRMCK201 Cs Cp LPVSS Figure 6: PLL Low Pass Filter Shielding This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 15 IRMCK203 Implementing the Low Pass Filter Shield Make all connections between CHGO, Rp, Cp, Cs and LPVSS as short as possible. Create the underlining shield by "copper filling" a larger area in the signal plane of the PCB. Connect this shield to the LPVSS pin of the IC. Do not connect this shield to signal ground (VSS). Cp Rp and Cs Component Values For a typical FR4 PCB, the values of the passive components are shown in Figure 7: PLL Low Pass Filter Values. COMPONENT Rp Cp Cs VALUE 3.9K 1000 Not Installed UNITS OHM pf Figure 7: PLL Low Pass Filter Values PLL Reset There are two reset pins on the IC, XPD and RESETN both low true. XPD holds the PLL circuitry in reset when low. Upon XPD going high, the PLL circuitry begins to lock onto the 33.33 MHz clock input. The PLL circuit may take up to 1 ms to become stable. RESETN asserted low holds the internal DSP logic in reset. Upon RESETN going high, the IC digital logic becomes active. RESET should be held low during and at least 1 ms after XPD goes high false to hold the internal logic in reset while the PLL becomes stable. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 16 IRMCK203 DC Electrical Characteristics and Operating Conditions Absolute Maximum Ratings Note: VSS = 0 Volt PARAMETER Power Supply Voltage Input Voltage SYMBOL VDD VI LIMITS VSS-0.3 to 4.0 VSS-0.3 to VDD+0.5 UNIT S V V NOTE Input Voltage VI VSS-0.3 to 7 V Non 5 Volt Tolerant Pins (Note 1) Only on 5 Volt Tolerant Pins (Note 1) Output Voltage Output Current per Pin Storage Temperature VO IOUT Tstg VSS-0.3 to VDD+0.5 +/- 30 -65 to 150 V mA C Table 3: Absolute Maximum Ratings Recommended Operating Conditions Note: VSS = 0 Volt PARAMETER Power Supply Voltage Input Voltage Input Voltage Ambient Temperature SYMBOL VDD VI VI Ta MIN 3.0 VSS VSS -40 TYP 3.3 MAX 3.6 VDD 5.5 85 UNITS V V V C NOTE Non 5 Volt Tolerant Pins (Note 1) Only on 5 Volt Tolerant Pins (Note 1) Note 2 Table 4: Recommended Operating Conditions Notes: 2. The ambient temperature range is recommended for Tj= -40 to 125 C This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 17 IRMCK203 DC Characteristics Common Quiescent and Leakage Current PARAMETER Quiescent Current SYMBOL IDDS CONDITIONS VI=VDD or VSS VDD=MAX IOH=IOL=0 Ta=Tj=85C VDD=MAX VIH=VDD VIL=VSS MIN TYP MAX .35 UNITS uA Input Leakage Current ILI -1 - 1 uA Table 5: DC Characteristics Input Characteristics - Non Schmitt Inputs PARAMETER High Level Input Voltage Low Level Input Voltage SYMBOL VIH1 VIL1 CONDITIONS VDD=MAX VDD=MIN MIN 2.0 TYP MAX 0.8 UNITS V V Table 6: Non Schmitt Input Characteristics Input Characteristics - Schmitt Inputs PARAMETER High Level Input Voltage Low Level Input Voltage Hysteresis Voltage SYMBOL VT1+ VT1VH1 CONDITIONS VDD=MAX VDD=MIN VDD=MIN MIN 1.1 0.6 0.1 TYP MAX 2.4 1.8 UNITS V V V Table 7: Schmitt Input Characteristics Output Characteristics PARAMETER High Level Output Voltage Low Level Output Voltage SYMBOL VOH3 VOL3 CONDITIONS VDD=MIN IOH=-12mA VDD=MIN IOH = 12mA MIN VDD - 0.4 TYP MAX VSS + 0.4 UNIT S V V Table 8: Output Characteristics This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 18 IRMCK203 Pin and I/O Characteristic Table Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pin Name INTERNAL IC RESISTOR TERMINATION 40K-240K Pull Down Pin Type I O I P O P I I P P P P O P I I I O O P O O O P O O P O O 20K - 120K Pull Down I 5.50 VOLT TOLERANT INPUT INPUT DC CHARACTERISTIC TABLE Table 7: Schmitt Input Characteristics OUTPUT DC CHARACTERISTIC TABLE Table 6: Non Schmitt Input Characteristics Table 6: Non Schmitt Input Characteristics - BYPASSMODE FLTCLROUT OSC1CLK LVDD OSC2CLK VSS PLLTEST XPD VSSHC MVDD VSSHC AVDD CHGO LPVSS DIR RESETN SPICSN REDLED GREENLED VSS PWMWL PWMWH PWMVL LVDD PWMVH PWMUL VSS PWMUH BRAKE BAUDSEL0 20K-120K Pull Down 20K - 120K Pull Down 20K -120K Pull Up YES - Table 7: Schmitt Input Characteristics Table 7: Schmitt Input Characteristics - Table 8: Output Characteristics Table 8: Output Characteristics Table 8: Output Characteristics Table 8: Output Characteristics Table 8: Output Characteristics Table 8: Output Characteristics Table 8: Output Characteristics Table 8: Output Characteristics Table 8: Output Characteristics - This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 19 IRMCK203 Pin Number 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 Pin Name INTERNAL IC RESISTOR TERMINATION 20K -120K Pull Up Pin Type I I I P O P I O I O I 20K -120K Pull Down I P O P O O O O O I O O 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down I I I P 5.50 VOLT TOLERANT INPUT YES YES YES YES YES YES YES YES YES YES INPUT DC CHARACTERISTIC TABLE Table 7: Schmitt Input Characteristics Table 7: Schmitt Input Characteristics Table 7: Schmitt Input Characteristics OUTPUT DC CHARACTERISTIC TABLE Table 8: Output Characteristics GATEKILL IFB1 IFB2 LVDD CLK1XOUT VSS SPIMOSI SPIMISO SPICLK TX RX BAUDSEL1 LVDD ADMUX0 VSS ADMUX1 ADMUX2 RESSAMPLE ADCONVST ADCLK ADOUT SYNC FAULT START/STOP ESTOP FLTCLR LVDD Table 7: Schmitt Input Characteristics Table 7: Schmitt Input Characteristics Table 7: Schmitt Input Characteristics Table 6: Non Schmitt Input Characteristics Table 7: Schmitt Input Characteristics Table 7: Schmitt Input Characteristics Table 7: Schmitt Input Characteristics Table 7: Schmitt Input Characteristics - Table 8: Output Characteristics Table 8: Output Characteristics Table 8: Output Characteristics Table 8: Output Characteristics Table 8: Output Characteristics Table 8: Output Characteristics Table 8: Output Characteristics Table 8: Output Characteristics Table 8: Output Characteristics Table 8: Output Characteristics - This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 20 IRMCK203 Pin Number 58 59 60 61 62 63 64 65 Pin Name INTERNAL IC RESISTOR TERMINATION Pin Type O O P O O O 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down 20K -120K Pull Down B B 5.50 VOLT TOLERANT INPUT INPUT DC CHARACTERISTIC TABLE Table 6: Non Schmitt Input Characteristics Table 6: Non Schmitt Input Characteristics Table 6: Non Schmitt Input Characteristics Table 6: Non Schmitt Input Characteristics Table 6: Non Schmitt Input Characteristics Table 6: Non Schmitt Input Characteristics Table 6: Non Schmitt Input Characteristics Table 6: Non Schmitt Input Characteristics Table 7: Schmitt Input Characteristics Table 7: Schmitt Input Characteristics Table 7: Schmitt Input Characteristics Table 7: Schmitt Input Characteristics Table 6: Non Schmitt Input Characteristics OUTPUT DC CHARACTERISTIC TABLE Table 8: Output Characteristics Table 8: Output Characteristics Table 8: Output Characteristics Table 8: Output Characteristics Table 8: Output Characteristics Table 8: Output Characteristics Table 8: Output Characteristics Table 8: Output Characteristics Table 8: Output Characteristics Table 8: Output Characteristics Table 8: Output Characteristics Table 8: Output Characteristics Table 8: Output Characteristics - PWMEN DAC3 VSS DAC2 DAC1 DAC0 HPD0 HPD1 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 HPD2 VDD HPD3 HPD4 VSS HPD5 HPD6 HPD7 HPOEN HPWEN HPA HPCSN VSS SCL SDA B P B B P B B B I I I I P O YES YES YES YES - - 20K -120K Pull Up B Table 8: Output Characteristics Table 8: Output Characteristics Table 9: Pin and I/O Characteristics This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 21 AC Electrical Characteristics and Operating Conditions System Level AC Characteristics Sync Pulse to Sync Pulse Timing t5 SYNC Current Feedback sampling t1 t2 t3 t4 Angle Estimation Closed loop current control Space Vector PWM Figure 8: System Level SYNC To SYNC Timing SYMBOL t1 t2 t3 t4 t5 DESCRIPTION Current Feedback Sample Delay from SYNC Pulse Falling Edge Angle Estimation Time Closed Loop Computation Time (current and velocity control) Space Vector PWM calculation time Total SYNC to SYNC minimum time TIME 4.3 4.9 3.1 2.3 14.6 UNITS us us us us us Table 10: System Level SYNC to SYNC Timing This document is the property of International Rectifier and may not be copied or distributed without expressed consent. IRMCK203 FAULT and REDLED Response to GATEKILL t5 GATEKILL t1 FAULT t2 REDLED t4 FLTCLR t3 Figure 9: FAULT and REDLED Response to GATEKILL SYMBOL t1 t2 t3 t4 t5 DESCRIPTION FAULT Response to GATEKILL REDLED Response to GATEKILL FAULT Response to FLTCLR REDLED Response to FLTCLR GATEKILL Pulse Width MIN TYP 685 715 145 175 UNITS ns ns ns ns ns 490 Table 11: FAULT and REDLED Response to GATEKILL This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 23 IRMCK203 Host Interface AC Characteristics SPI Timing tSCLK SCLK CS tCSS tMOSIS MOSI MISO tMISO tMISOZ Figure 10 SPI Timing SYMBOL fSCLK tSCLK tCSS tMOSIS tMISO tMIOZ DESCRIPTION SPI Clock Frequency SPI Clock Period CS to SCLK high Setup MOSI to SCLK low Setup SCLK to MISO Valid CS to MOSI High Impedance MIN 125 20 20 30 15 MAX 8 35 UNITS MHz ns ns ns ns ns Table 12: SPI Timing This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 24 IRMCK203 Host Parallel Timing Host Parallel Read Cycle tHPCSN HPCSN HPWEN tHPWENS tHPA tHPAS tAHPD HPA HPD[7:0] tHPOENS HPOEN tHPOENH tHPZD tHPOEN VALID tHPDZ Figure 11: Host Parallel Read Cycle SYMBOL tHPCSN tHPWENS tHPAS tAHPD THPZD tHPDZ tHPOENH tHPOENS tHPOEN DESCRIPTION HPCSN Period HPWENS Setup HPA Setup HPD[7:0] Access HPD[7:0] Active HPD[7:0] High Impedance HPOEN Hold HPOEN Setup HPOEN Period MIN 70 10 10 60 0 0 10 10 70 MAX 105 9 6 UNIT S ns ns ns ns ns ns ns ns ns NOTE Note 3 Note 3 Table 13: Host Parallel Read Cycle Timing Note: 3. HPOEN must be stable before and after the high to low transition of HPCNS. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 25 IRMCK203 Host Parallel Write Cycle tHPCSN HPCSN tHPWENS HPWEN tHPAS tHPWEN tHPA HPD[7:0] tHPD[7:0]S HPOEN tHPOENS tHPD[7:0] tHPOEN Figure 12: Host Parallel Write Cycle SYMBOL tHPCSN tHPWENS tHPWEN tHPAS tHPA tHPD[7:0] tHPOENS tHPOEN DESCRIPTION HPCSN Period HPWENS Setup HPWEN Period HPA Setup HPA Period HPD[7:0] Setup HPOEN Setup HPOEN Period MIN 70 10 70 -10 70 -10 10 70 MAX UNITS ns ns ns ns ns ns ns ns NOTE Note 4 Table 14: Host Parallel Write Cycle Timing Note: 4. HPOEN must be asserted high while HPCSN low during a Host Parallel Write Cycle. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 26 IRMCK203 Discrete I/O Electrical Characteristics FBCAL START STOP FLTCLR tL Figure 13: Discrete I/O Timing SYMBOL tL DESCRIPTION Pulse Width FBCAL Pulse Width START Pulse Width STOP Pulse Width FLTCLR MIN 100 100 100 1 Table 15: Discrete I/O Timing MAX UNITS ms ns ns us This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 27 IRMCK203 Motion Peripheral Electrical Characteristics PWM Electrical Characteristics Error! Not a valid link. Figure 14: PWM Timing SYMBOL tDEADTIMERESOLUTION DESCRIPTION Deadtime Insertion Logic Resolution Table 16: PWM Timing 30 UNITS ns IR2175 Interface tIFB tIFBH IFB0 IFB1 tIFBL Figure 15: IR2175 Interface SYMBOL fIFB tIFB tIBH tIFBH DESCRIPTION Current Feedback Input Frequency Current Feedback Period Current Feedback High Pulse Width Current Feedback Low Pulse Width MIN 95 10.52 500 ns 500 ns MAX 165 6.06 10 us 10 us UNITS kHz us Table 17: IR2175 Interface This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 28 Analog Interface Electrical Characteristics ADC Timing System Level Timing The IRMCK203 contains logic to drive an ADC Converter, Analog MUX and associated Sample and Hold circuits. Figure 16: Top Level ADC Timing shows the system level timing of these elements. Figure 17: ADC Specific Timing shows specific timing parameters associated with the ADC Converter. Refer to the Application Developers Guide for a detailed description of ADC, MUX and Sample and Hold signal system level protocol. tSYNC SYNC RESSAMPLE ADCONVST ADMUX0 tADCONVST tADMUX ADMUX1 ADCLK tADMUX1S tADCLK tADCLK Figure 16: Top Level ADC Timing SYMBOL tSYNC tRESSAMPLES tADMUX0S tADMUX1S tADCONVSTS DESCRIPTION SYNC Pulse Width SYNC Falling Edge to RESSAMPLE Valid ADCONVST to ADMUX0 Valid ADCONVST to ADMUX1 Valid ADCONVST to ADCLK MIN -10 40 40 71 TYP 3 MAX 10 61 61 91 UNITS us ns ns ns ns Table 18: Top Level ADC Timing This document is the property of International Rectifier and may not be copied or distributed without expressed consent. IRMCK203 Converter Level Timing t1 ADCLK tADOUTS ADOUT t2 ADCONVST D11 tHADOUT D10 D2 D1 D0 tADCLK RESSAMPLE t3 ADMUX0 ADMUX1 Figure 17: ADC Specific Timing SYMBOL FADCLK tADCLK t1 t2 t3 tHADOUT tADOUTS DESCRIPTION SPI Clock Frequency SPI Clock Period RESSAMPLE to ADCLK RESSAMPLE to ADCONVST RESSAMPLE to ADMUX0, ADMUX1 ADOUT to ADCLK Setup ADOUT to ADCLK Hold MIN 8.33 120 MAX 91 40 64 19.7 2 UNITS MHz ns ns ns ns ns Table 19: ADC Specific Timing This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 30 PLL Interface Electrical Characteristics PARAMETER Current Consumption Current Consumption Peak jitter Cycle jitter Lock-up Time PLL Reset Period SYMBOL IDDS IDD Tpj Tcj Tlock Trst CONDITION S Static Dynamic Recommended operating condition MIN -500 10 TYP 5 MAX 170 1000 +500 1 UNITS uA MA ps ps ms ns Table 20: PLL Electrical Characteristics This document is the property of International Rectifier and may not be copied or distributed without expressed consent. IRMCK203 Appendix A Register Access A host computer controls the IRMCK203 using either its slave-mode Full-Duplex SPI port, or a standard RS-232 port. Both interfaces are always active and can be used interchangeably, although not simultaneously. Control/status registers are mapped into a 128-byte address space. Host Register Map SPI Register Access When configured as an SPI device read only and read/write operations are performed using the following transfer format: ................ Command Byte Data Byte 0 Data Byte N Data Transfer Format 7 Read Only 6 5 Bit Position 4 3 2 1 0 Register Map Starting Address Command Byte Format Data transfers begin at the address specified in the command byte and proceed sequentially until the SPI transfer completes. Note that accesses are read/write unless the "read only" bit is set. RS-232 Register Access The IRMCK203 includes an RS-232 interface channel that provides a direct connection to the host PC. The software interface combines a basic "register map" control method with a simple communication protocol to accommodate potential communication errors. RS-232 Register Write Access A Register write operation consists of a command/address byte, byte count, register data and checksum. When the IRMCK203 receives the register data, it validates the checksum, writes the register data, and transmits and acknowledgement to the host. Command / Address Byte Byte Count 1-6 bytes of register data Checksum Register Write Operation Command Acknowledgement Byte Checksum Register Write Acknowledgement Bit Position This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 32 IRMCK203 7 1=Read/ 0=Write 6 5 4 3 2 1 0 Register Map Starting Address Command/Address Byte Format 7 1=Error/ 0=OK 6 5 Bit Position 4 3 2 1 0 Register Map Starting Address Command Acknowledgement Byte Format The following example shows a command sequence sent from the host to the IRMCK203 requesting a two-byte register write operation: 0x2F Write operation beginning at offset 0x2F 0x02 Byte count of register data is 2 0x00 Data byte 1 0x04 Data byte 2 0x35 Checksum (sum of preceding bytes, overflow discarded) A good reply from the IRMCK203 would appear as follows: 0x2F Write completed OK at offset 0x2F 0x2F Checksum An error reply to the command would have the following format: 0xAF Write at offset 0x2F completed in error 0xAF Checksum RS-232 Register Read Access A register read operation consists of a command/address byte, byte count and checksum. When the IRMCK203 receives the command, it validates the checksum and transmits the register data to the host. Command / Address Byte Byte Count Checksum Register Read Operation Command Acknowledgement Byte Register Data (Byte Count bytes) Checksum Register Read Acknowledgement (transfer OK) This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 33 IRMCK203 Command Acknowledgement Byte Checksum Register Read Acknowledgement (error) The following example shows a command sequence sent from the host to the IRMCK203 requesting four bytes of read register data: 0xA0 Read operation beginning at offset 0x20 (high-order bit selects read operation) 0x04 Requested data byte count is 4 0xA4 Checksum A good reply from the IRMCK203 might appear as follows: 0x20 Read completed OK at offset 0x20 0x11 Data byte 1 0x22 Data byte 2 0x33 Data byte 3 0x44 Data byte 4 0xCA Checksum An error reply to the command would have the following format: 0xA0 Read at offset 0x20 completed in error 0xA0 Checksum RS-232 Timeout The IRMCK203 receiver includes a timer that automatically terminates transfers from the host to the IRMCK203 after a period of 32 msec. RS-232 Transfer Examples The following example shows a normal exchange executing a register write access. Host Write Request Data... FPGA Perform write operation ACK (OK) Request complete The example below shows a normal register read access exchange. Host Read Request Perform read operation ACK (OK) Data... Request complete FPGA This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 34 IRMCK203 The following example shows a register write request that is repeated by the host due to a negative acknowledgement from the IRMCK203. Host Write Request Data... Error in processing (e.g., bad checksum) ACK (error) resend Write Request Data... Perform write operation ACK (OK) Request complete FPGA In the final example, the host repeats a register read access request when it receives no response to its first attempt. Host Read Request FPGA ... time out, resend Read Request Perform read operation ACK (OK) Data... Request complete This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 35 IRMCK203 Write Register Definitions PwmConfig Register Group (Write Registers) Byte Offset 7 0xC 0xD 0xE 0xF 0x44 0x45 TwoPhs Pwm (W) TwoPhs Type (W) Gatekill Sns (W) 6 SPARE 5 Gate SnsL (W) Bit Position 4 3 Gate SnsU (W) SyncSns 2 BrakeSns 1 SPARE 0 SPARE PwmPeriod (LSBs) (W) PwmConfig (W) PwmDeadTm (W) ModScl (LSBs) (W) ModScl (MSBs) (W) PwmPeriod (MSBs) (W) PwmConfig Write Register Map Field Name BrakeSns SyncSns GateSnsU GateSnsL GatekillSns PwmPeriod PwmConfig TwoPhsType Access (R/W) W W W W W W W W Field Description Logic Sense for BRAKE signal output to gate driver IC. 0 = Active low, 1 = active high. Logic Sense for PWM SYNC signal output to microprocessor. 0 = Active low, 1 = active high. Upper IGBT gate sense. 1 = active high gate control, 0 = active low gate control. Lower IGBT gate sense. 1 = active high gate control, 0 = active low gate control. GATEKILL signal sense. 1 = active high GATEKILL, 0 = active low GATEKILL. PWM Carrier period. Actual PWM carrier period is 2 * (PwmPeriod + 1) * (System Clock Period). PWM Configuration. 0 = Asymmetrical center aligned PWM, 1 = Symmetrical Center aligned PWM. Used only for two-phase PWM modulation mode: 0 = Type 1 2-phase PWM 1 = Type 2 2-phase PWM Selects PWM modulation mode: 0 = Enable 3-phase space vector PWM modulation 1 = Enable 2-phase space vector PWM modulation Gate drive dead time in units of system clock cycles (e.g., 30 ns with 33 MHz clock). TwoPhsPwm W PwmDeadTm W This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 36 IRMCK203 Field Name Access (R/W) Field Description ModScl Space vector modulator scale factor. This register, which depends on the PWM carrier frequency, should be set as follows: W ModScl = PwmPeriod * sqrt(3) * 4096 / 2355 where PwmPeriod is the value in the PwmConfig write register group's PwmPeriod register. PwmConfig Write Register Field Definitions CurrentFeedbackConfig Register Group (Write Registers) Byte Offset 7 0x10 0x11 0x12 0x15 0x16 IfbOffsW (LSBs) (W) IfbOffsW (MSBs) (W) IfbkScl (LSB) (W) IfbkScl (MSB) (W) 6 5 Bit Position 4 3 IfbOffsV (LSBs) (W) 2 1 0 IfbOffsV (MSBs) (W) CurrentFeedbackConfig Write Register Map Field Name IfbOffsV Access (R/W) W Field Description IfbOffsW IfbkScl 12-bit signed value for V phase current feedback offset. When the IfbOffsEnb bit in the SystemControl write register group is "0" this value is automatically added to each current measurement in hardware. 12-bit signed value for W phase current feedback offset. . When W the IfbOffsEnb bit in the SystemControl write register group is "0" this value is automatically added to each current measurement in hardware. Rotating frame Iq component and Id component current feedback W scale factor. Constant used to scale current measurements before they are used in the field orientation calculation. This is a 15-bit fixedpoint signed number with 10 fractional bits that ranges from -16 to + 16 + 1023 / 1024. CurrentFeedbackConfig Write Register Field Definitions This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 37 IRMCK203 SystemControl Register Group (Write Registers) Byte Offset 7 0x17 SPARE 6 IfbOffs Enb 5 Bit Position 4 3 SPARE 2 AdcIfb Enb 1 StartCmd 0 SPARE SystemControl Write Register Map Field Name StartCmd Access (R/W) W Field Description AdcIfbEnb IfbOffsEnb Start/Stop bit. Setting this bit to 1 issues a start command. Setting this bit to 0 stops the motor. A/D Converter IFB Enable. Setting this bit to "1" causes current W feedback measurement to be taken from the ADS7818 A/D converter interface. When IFB PwmEnbW = 1, and FocEnbW = 0, the Current feedback offset is calculated and saved in the CurrentFeedbackOffset read register group. When IfbOffsEnb = 1, the Current feedback offset W values in the CurrentFeedbackOffset Read registers are applied to each current feedback measurement. When IfbOffsEnb = 0, the Current feedback offset values in the CurrentFeedbackConfig Write registers are applied to each current feedback measurement. SystemControl Write Register Field Definitions TorqueLoopConfig Register Group (Write Registers) Byte Offset 7 0x1A 0x1B 0x1C 0x1D 0x22 0x23 0x26 6 5 Bit Position 4 3 2 1 0 KpIreg - Current Loop Proportional Gain (LSBs) (W) KpIreg - Current Loop Proportional Gain (MSBs) (W) KxIreg - Current Loop Integral Gain (LSBs) (W) KxIreg - Current Loop Integral Gain (MSBs) (W) VqLim - Quadrature Current Output Limit (LSBs) (W) VqLim - Quadrature Current Output Limit (MSBs) (W) VdLim - Direct Current Output Limit (LSBs) (W) This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 38 IRMCK203 Byte Offset 7 0x27 6 5 Bit Position 4 3 2 1 0 VdLim - Direct Current Output Limit (MSBs) (W) TorqueLoopConfig Write Register Map Field Name KpIreg KxIreg VqLim VdLim Access (R/W) W W W W Field Description 15-bit signed current loop PI controller proportional gain. Scaled with 14 fractional bits for an effective range of 0 - 1. 15-bit signed current loop PI controller integral gain. Scaled with 19 fractional bits for an effective range of 0 - .03125. 16-bit Quadrature current PI controller voltage output limit. 16-bit Direct current PI controller voltage output limit. TorqueLoopConfig Write Register Field Definitions VelocityControl Register Group (Write Registers) Byte Offset 7 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 6 5 Bit Position 4 3 2 1 0 KpSreg - Velocity loop proportional gain (LSBs) (W) KpSreg - Velocity loop proportional gain (MSBs) (W) KxSreg - Velocity loop integral gain (LSBs) (W) KxSreg - Velocity loop integral gain (MSBs) (W) MotorLim - Velocity loop Output Positive Limit (LSBs) (W) MotorLim - Velocity loop Output Positive Limit (MSBs) (W) RegenLim - - Velocity loop Output Negative Limit (LSBs) RegenLim - - Velocity loop Output Negative Limit (MSBs) SpdScl - Speed Scale Factor (LSBs) SpdScl - Speed Scale Factor (MSBs) TargetSpd - Setpoint/target speed (LSBs) This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 39 IRMCK203 Byte Offset 7 0x3D 0x3E 0x3F 0x7A 0x18 0x19 6 5 Bit Position 4 3 2 1 0 TargetSpd - Setpoint/target speed (MSBs) AccelRate DecelRate MinSpd StartLim (LSBs) StartLim (MSBs) VelocityControl Write Register Map Field Name KpSreg KxSreg MotorLim RegenLim Access (R/W) W W W W Field Description SpdScl W TargetSpd AccelRate DecelRate MinSpd StartLim W W W W W 15-bit velocity loop proportional gain, in fixed point with 5 fractional bits. Range = 0 - 512. 15-bit velocity loop integral gain, in fixed point with 13 fractional bits. Range = 0 - 2. 16-bit speed PI controller output positive limit. 16-bit speed PI controller output negative limit (2's complement). Motor Speed Scale factor. Spd value (in the VelocityStatus read register group) is maintained in SPEED units of SpdScl * (Encoder counts / Velocity Loop Execution) or SpdScl * (RATE * Encoder counts / PWM period). The user should set SpdScl = (64 * 16384) * 60 * PWMFREQ / (RATE * Max RPM * Encoder counts/revolution), which will result in a Spd value ranging 16384 corresponding to Max RPM. Velocity loop speed setpoint in SPEED units, which are determined by the user via the SpdScl register setting. Positive speed rate limit. Negative speed rate limit. Minimum speed protection. This parameter sets the minimum reference speed. Drive start-up current limit. VelocityControl Write Register Field Definitions This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 40 IRMCK203 FaultControl Register Group (Write Registers) Byte Offset 7 0x42 6 5 SPARE Bit Position 4 3 2 1 FltClr 0 DcBusM Enb FaultControl Write Register Map Field Name Access (R/W) Field Description DC Bus monitor enable. 1 = Monitor DC bus voltage and generate appropriate brake signal control and disable PWM output when voltage fault conditions occur. GatekillFlt and OvrSpdFlt faults cannot be disabled. DC bus voltage thresholds are as follows: Overvoltage - 410V Brake On - 380V Brake Off - 360V Nominal - 310V Undervoltage off - 140V Undervoltage - 120V This bit clears all active fault conditions. The user should monitor the FaultStatus read register group to determine fault status and set this bit to "1" to clear any faults that have occurred. A fault condition automatically clears the PwmEnbW and FocEnbW bits in the SystemControl write register group. Note that this bit also directly controls the output 2137 FLTCLR pin. After clearing a fault, the user must explicitly set this bit to "0" to re-enable fault processing. FaultControl Write Register Field Definitions DcBusMEnb W FltClr W SystemConfig Register Group (Write Registers) Byte Offset 7 0x50 ExtCtrl 6 SpdRef Sel 5 Ramp Stop Bit Position 4 3 2 SPARE 1 0 SystemConfig Write Register Map Field Name RampStop Access (R/W) W Field Description Selects the stopping mode: 0 - Configure for Coast stopping 1 - Configure for Ramp stopping This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 41 IRMCK203 Field Name SpdRefSel Access (R/W) W Field Description ExtCtrl Selects the source for the Speed PI controller reference input: 0 = Use internal speed reference 1 = Use external speed reference Setting this bit to "1" enables direct control of basic motor operation W via the external User Interface pins. When this bit is "1", the FocEnbW and PwmEnbW bits in the SystemControl write register group are ignored. SystemConfig Write Register Field Definitions EepromControl Registers (Write Registers) At power up, the write registers can be optionally initialized with values stored in EEPROM. The EepromControl write register group and EepromStatus read register group are used to read and write these EEPROM values. Since the EeAddrW write register (which selects the EEPROM offset to read or write) does not require initialization at power up, the location corresponding to that register in EEPROM (at offset 0x5D) is used to store a register map version code. At power on, the IRMCK203 initializes the write registers from EEPROM only if the version code stored at this offset in EEPROM matches its internal register map version code (which can be read from the RegMapVer field of the EepromStatus read register group). To enable write register initialization at power up, write the appropriate register map version code to EEPROM at offset 0x5D. To disable write register initialization at power up, write a zero (or any non-matching version code) to offset 0x5D of the EEPROM. Byte Offset 7 0x5C 0x5D 0x5E 6 5 SPARE Bit Position 4 3 2 EeWrite 1 EeRead 0 EeRst EeAddrW / RegMapVersCode (W) EeDataW (W) EepromControl Write Register Map Field Name EeRst EeRead Access (R/W) W W Field Description Self-clearing EEPROM reset. Writing a "1" to this bit resets the I2C EEPROM interface. Self-clearing I2c EEPROM Read. Writing a "1" to this bit initiates an EEPROM read from the byte located at EEPROM address EeAddrW. After setting this bit the user should poll the EeBusy bit in the EepromStatus read register group to determine when the read completes and then read the data from EeDataR in the EepromStatus read register group. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 42 IRMCK203 Field Name EeWrite Access (R/W) W Field Description EeAddrW EeDataW Self-clearing EEPROM Write. Writing a "1" to this bit initiates an EEPROM write from the data byte in EeDataW to the EEPROM address EeAddrW . W EEPROM Address Register. Contains the address for the next EEPROM read or write operation. W EEPROM Data Register. Contains the data for the next EEPROM write operation. EepromControl Write Register Field Definitions ClosedLoopAngleEstimator Registers (Write Registers) Byte Offset 7 0x60 0x61 0x62 0x63 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 SPARE SPARE 6 5 Bit Position 4 3 IScl (LSBs) (W) IScl (MSBs (W) FlxBInit (LSBs) (W) FlxBInit (MSBs) (W) PllKp (LSBs) (W) 2 1 0 PllKp (MSBs (W) PllKi (LSBs) (W) PllKi (MSBs (W) VoltScl (LSBs) (W) VoltScl (MSBs (W) Rs (LSBs) (W) Rs (MSBs (W) Ld (LSBs) (W) Ld (MSBs (W) This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 43 IRMCK203 Byte Offset 7 0x74 0x75 0x76 0x77 SPARE 6 5 Bit Position 4 3 AtanTau (LSBs) (W) AtanTau (MSBs (W) FlxTau (LSBs) (W) 2 1 0 FlxTau (MSBs) (W) ClosedLoopAngleEstimator Write Register Map Field Name IScl FlxBInit PllKp PllKi VoltScl Rs Ld AtanTau FlxTau Access Field Description (R/W) W Current scaler for motor flux calculation. W Initialization value of Beta flux at start. W Flux phase lock loop proportional gain. W Flux phase lock loop integral gain. W Voltage scaler for motor flux calculation. W Motor per phase resistance including cable (@25C). W Motor per phase inductance. W Rotor angle estimator phase compensation gain. W Rotor angle estimator flux model time constant. ClosedLoopAngleEstimator Write Register Field Definitions OpenLoopAngleEstimator Registers (Write Registers) Byte Offset 7 0x66 0x67 6 5 Bit Position 4 3 KTorque (LSBs) (W) KTorque (MSBs (W) 2 1 0 OpenLoopAngleEstimator Write Register Map Field Name KTorque Access Field Description (R/W) W Motor mechanical model torque constant. OpenLoopAngleEstimator Write Register Field Definitions This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 44 IRMCK203 StartupAngleEstimator Registers (Write Registers) Byte Offset 7 0x64 0x65 0x68 0x69 0x78 DacSel Zero SpdFlt Disable Use2xFrq Scale SPARE 6 5 Bit Position 4 3 ParkI (W) 2 1 0 DiagnosticCtrl (W) WeThr (LSBs) (W) WeThr (MSBs (W) ParkTm (W) StartupAngleEstimator Write Register Map Field Name ParkI DiagnosticCtrl Access (R/W) W W Field Description Use2xFrqScale ZeroSpdFlt Disable DacSel WeThr ParkTm DC current injection level during motor parking (start-up mode). 1 (0001) - Enable Parking diagnostic 2 (0010) - Enable start-up diagnostic 5 (0101) - Enable current regulator diagnostic 9 (1001) - Enable volts Hertz diagnostic W Selects speed scaling: 0 - Norminal speed scale 1 - Reduce speed feedback scaling by half W Zero speed fault enable/disable: 0 - Enbale Zero Speed Fault 1 - Disable Zero Speed Fault W Selects D/A converter diagnostic outputs 0 - 3. A value of 0 selects: Data 0 = Alpha flux Data 1 = Electrical angle Data 2 = Alpha voltage Data 3 = Closed loop/open loop mode (0 = open, 1 = closed) A value of 1 selects: Data 0 = Alpha current Data 1 = Torque current feedback Data 2 = IQ ref Data 3 = Motor speed W Frequency threshold level (switch over from open-loop to closedloop mode). W Time duration of parking mode. StartupAngleEstimator Write Register Field Definitions This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 45 IRMCK203 TraceBufferControl Register Group (Write Registers) The Trace Buffer Control Register group manages the IRMCK203 diagnostic trace function. The IRMCK203 contains an internal circular trace buffer consisting of 2048 four-byte entries. Each entry consists of two 16-bit items of sampled data: configurable data item "A" and configurable data item "B". Data is read from the trace buffer using the Trace Buffer Status Read Register group. To use the trace function without the trigger: 1. Write a "1" to the TrcRst bit to reset the trace. 2. Select "A" and "B" data items by writing to the TrcDataASel and TrcDataBSel registers. 3. Specify the number of samples to be collected (1 - 2048) by writing to the PstTrigCnt register. 4. Set TrigEdge to zero. 5. Set the Arm and ForceTrig bits to start collecting data and generate an immediate trigger so collection will stop after PstTrigCnt samples. 6. Read TrcSt (in the TraceBufferStatus read Register group) until its value is 3 (done collecting data). 7. Read TrcDataA and TrcDataB (in the TraceBufferStatus read Register group) 2048 times to retrieve the entire trace buffer. The valid samples are in the last PstTrigCnt buffer entries retrieved. NOTE: To read the data samples properly, you must either read each TrcDataA and TrcDataB together in a single 32-bit operation, or read each TrcDataB first, before reading TrcDataA. This is because the IRMCK203 internal trace buffer pointer increments to the next sample on a read of TrcDataA (LSBs). To use the trace with trigger: 1. Write a "1" to the TrcRst bit to reset the trace. 2. Select "A" and "B" data items by writing to the TrcDataASel and TrcDataBSel registers. (The trigger is always based on the data "A" item.) 3. Specify the number of samples to be collected after the trigger occurs (1 - 2048) by writing to the PstTrigCnt register. 4. Set TrigLvl to the value of data item "A" at which you want the trigger to occur. 5. Set TrigEdge to 1 or 2 depending on whether you want the trigger to occur on the falling or rising edge of the data item "A" value. 6. Set the Arm bit to start collecting data. (Do not set the ForceTrig bit.) 7. When the trigger occurs, the value of TrcSt (in the TraceBufferStatus Read Register group) changes to 2. Read TrcSt until its value changes to 3 (done collecting data). 8. Read TrcDataA and TrcDataB (in the TraceBufferStatus read Register group) 2048 times to retrieve the entire trace buffer. The oldest samples are retrieved first, so the samples collected after the trigger occurred are in the last PstTrigCnt buffer entries. NOTE: To read the data samples properly, you must either read each TrcDataA and TrcDataB together in a single 32-bit operation, or read each TrcDataB first, before reading TrcDataA. This is because the IRMCK203 internal trace buffer pointer increments to the next sample on a read of TrcDataA (LSBs). Byte Offset 7 0x2B 0x2C 0x2D 0x2E 0x2F TrcRst Arm ForceTrig SPARE 6 TrigEdge 5 Bit Position 4 3 2 SPARE 1 0 PstTrigCnt (LSBs) PstTrigCnt (MSBs) TrcDataBSel TrcDataASel TrigLvl (LSBs) This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 46 IRMCK203 Byte Offset 7 0x30 6 5 Bit Position 4 3 TrigLvl (MSBs) 2 1 0 TraceBufferControl Write Register Map Field Name TrigEdge PstTrigCnt Access (R/W) W Field Description ForceTrig Arm TrcRst TrcDataASel, TrcDataBSel TrigLvl Trigger edge for threshold level triggering. 0 = Disabled, 1 = Rising edge, 2 = Falling edge. W Post Trigger count. Specifies number of samples to collect immediately following a trace trigger occurrence. Force trace trigger. Setting this self-clearing bit to 1 initiates a trace W trigger, which causes data collection to cease immediately after another PstTrigCnt samples. W Trace arm. Setting this self-clearing bit to 1 starts data collection to the circular trace buffer. W Trace reset. Setting this self-clearing bit to 1 resets the trace state to Idle. Selects data items for display on channels "A" and "B": 1 = DC Bus voltage 2 = V phase current 3 = W phase current 4 = Flx_M 5 = Speed PI reference W 6 = Speed PI feedback 7 = Alpha flux 8 = IQ Ref 9 = Q axis voltage Qv 10 = D axis voltage Dv 11 = 12-bit electrical angle 12 = Q axis current Qi 13 = D axis current Di 14 = Alpha current 15 = Beta current Trigger threshold level. When this field is non-zero, a trace trigger is W initiated each time the channel "A" data passes through this value as indicated by the TrigEdge field. TraceBufferControl Write Register Field Definitions This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 47 IRMCK203 StartupRetrail Registers (Write Registers) Byte Offset 7 0x79 0x7B 0x7C 0x7D 0x7E 0x7F FlxThrH 6 5 Bit Position 4 3 ParkTmRet 2 1 0 FlxThrL RetryTm NumRetries ParkIRet StartupRetrail Write Register Map Field Name ParkTmRet Access (R/W) W Field Description FlxThrL FlxThrH RetryTm NumRetries W W W W ParkIRet W Start-up failure may be caused by increased shaft friction. After first start-up retry, the parking time can be increased to improve parking performance. The low flux threshold level for determining a successful startup. The high flux threshold level for determining start-up failure. This parameter provides the adjustment to the retry sampling instant. The sampling instant starts when Closed_Loop = 1. If start-up fails, the user can program start-up retrial. This parameter determines the number of start-up retries. A value of zero will disable startup retrial. The maximum number of retries is 15. Start-up failure may be caused by increased shaft friction. After first start-up retry, the parking current can be increased to improve parking performance. StartupRetrail Write Register Field Definitions This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 48 IRMCK203 Read Register Definitions SystemStatus Register Group (Read Registers) Byte Offset 7 0x7 StartStop 6 FwdRev 5 SPARE Bit Position 4 3 PwrID 2 ExtCtrlR 1 Foc EnbR 0 Pwm EnbR SystemStatus Read Register Map Field Name PwmEnbR FocEnbR ExtCtrlR PwrID FwdRev Access (R/W) R R R R R Field Description StartStop R PWM Enable bit status. FOC Enable bit status. Reflects the status of the ExtCtrl bit in the System Configuration write register (address 0x50). Power ID. 0 = 3 kW, 1 = 2 kW, 2 = 500 W. User Interface "FWD/REV" digital input status. 1 - Forward rotation request 0 - Reverse rotation request User Interface "START/STOP" digital input status. 1 - Start 0 - Stop SystemStatus Read Register Field Definitions DcBusVoltage Register Group (Read Registers) Byte Offset 7 0xA 0xB SPARE 6 5 Bit Position 4 3 DcBusVolts (LSBs) 2 1 0 Brake DcBusVolts (MSBs) DcBusVoltage Read Register Map This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 49 IRMCK203 Field Name DcBusVolts Brake Access (R/W) R R Field Description DC Bus Voltage. Data range is 0 - 4095, which corresponds to a DC bus voltage between 0 and 500 volts. Brake signal status. 1 = Brake signal active. DcBusVoltage Read Register Field Definitions FocDiagnosticData Register Group (Read Registers) Byte Offset 7 0xC 0xD 0xE 0xF 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 6 5 Bit Position 4 3 2 1 0 IvFbk - V Phase IFB Raw Current (LSBs) (R) IwFbk - W Phase IFB Raw Current (LSBs) (R) IvFbk - V Phase IFB Raw Current (MSBs) (R) IwFbk - W Phase IFB Raw Current (MSBs) (R) Id - Synchronous Frame Direct Current (LSBs) (R) Id - Synchronous Frame Direct Current (MSBs) (R) Iq - Synchronous Frame Quadrature Current (LSBs) (R) Iq - Synchronous Frame Quadrature Current (MSBs) (R) Ud - Synchronous Frame Direct Voltage (LSBs) (R) Ud - Synchronous Frame Direct Voltage (MSBs) (R) Uq - Synchronous Frame Quadrature Voltage (LSBs) (R) Uq - Synchronous Frame Quadrature Voltage (MSBs) (R) UAlpha - Stationary Frame Alpha Voltage (LSBs) (R) UBeta - Stationary Frame Beta Voltage (LSBs) (R) UAlpha - Stationary Frame Alpha Voltage (MSBs) (R) UBeta - Stationary Frame Beta Voltage (MSBs) (R) FocDiagnosticData Read Register Map This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 50 IRMCK203 Field Name IvFbk, IwFbk Access (R/W) R Field Description Id, Iq Ud, Uq UAlpha, UBeta Offset-corrected V and W phase raw current from the IR2175 current sensor. Values range from 0 - 4096, where 2048 corresponds to 0 current. The current feedback scale factors IdScl and IqScl in the CurrentFeedbackConfig write register group and the current sense resistor value determine the full scale current value. Synchronous or rotating frame direct and quadrature current values R in 2's complement representation. The full scale current values range from -16384 to 16383. Synchronous or rotating frame direct and quadrature voltage values R in 2's complement representation. Data ranges are VdLim for Ud and VqLim for Uq as specified in the TorqueLoopConfig write register group. R Stationary frame Alpha and Beta voltage output component values. Data range is VdLim or VqLim (as specified in the TorqueLoopConfig write register group), whichever is larger. FocDiagnosticData Read Register Field Definitions FaultStatus Register Group (Read Registers) The Fault Status register records fault conditions that occur during drive operation. When any of these fault conditions occur, the PWM output is automatically disabled. The user should monitor this register continuously for fault conditions. A fault condition can be cleared by writing a "1" to the FaultClr bit in the FaultControl write register group. (This does not automatically re-enable PWM output.) Byte Offset 7 0x1E SPARE 6 RetryFlt 5 ZeroSpd Flt Bit Position 4 3 ExecTm Flt OvrSpdFlt 2 OvFlt 1 LvFlt 0 GatekillFlt FaultStatus Read Register Map Field Name GatekillFlt LvFlt OvFlt Access (R/W) R R R Field Description Filtered and latched version of IR213x FAULT output. DC bus low voltage fault. This fault occurs if the DC bus drops below 120V. DC bus overvoltage fault. This fault occurs if the DC bus voltage exceeds 410V. Over speed fault. This fault occurs whenever the motor reaches the positive or negative limits. The user should use the scale factor in the SpdScl field of the VelocityControl write register group to scale the motor speed so that it falls between -16384 and +16383 with these limits as the over speed condition. Execution time fault. OvrSpdFlt R ExecTmFlt R This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 51 IRMCK203 Field Name ZeroSpdFlt Access (R/W) R Field Description Zero Speed fault. When speed is less than MinSpd/2 (half minimum speed) for a continous period of 2 seconds, the zero speed fault will be set. Start-up retry fault. After a certain number (determined by parameter NumRetries) of start-up failures, this fault will be set. FaultStatus Read Register Field Definitions RetryFlt R VelocityStatus Register Group (Read Registers) Byte Offset 7 0x26 0x27 6 5 Bit Position 4 3 Spd (LSBs) 2 1 0 Spd (MSBs) VelocityStatus Read Register Map Field Name Spd Access (R/W) R Field Description Current motor speed in SPEED units. (See the description of SpdScl in the VelocityControl write register group.) VelocityStatus Read Register Field Definitions CurrentFeedbackOffset Register Group (Read Registers) Byte Offset 7 0x30 0x31 0x32 IfbWOffs (LSBs) (R) IfbWOffs (MSBs) (R) 6 5 Bit Position 4 3 IfbVOffs (LSBs) (R) 2 1 0 IfbVOffs (MSBs) (R) CurrentFeedbackOffset Read Register Map This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 52 IRMCK203 Field Name IfbVOffs, IfbWOffs Access (R/W) R Field Description Current feedback offset values from the last IFB Offset calculation. These values are automatically applied to each current feedback measurement value whenever the IfbOffsEnb bit in the SystemControl write register group is set. CurrentFeedbackOffset Read Register Field Definitions EepromStatus Registers (Read Registers) Byte Offset 7 0x38 0x39 0x3A 6 5 Bit Position 4 3 SPARE 2 1 0 EeBusy EdDataR (R) EeAddrR (R) EepromStatus Read Register Map Field Name EeBusy EeDataR Access (R/W) R R Field Description EeAddrR R I2C EEPROM Interface busy bit. The user should wait for this bit to clear before initiating EEPROM read or write operations. EEPROM Data Register. Contains the data from the last EEPROM read operation. Note that writing to the EeRst field in the EepromControl write register group invalidates this register. EEPROM Address read register shows the value stored in EEPROM at the offset of the EeAddrW write register (0x5D). Since this address in the EEPROM contains the IRMCK203 register map version, the user can read this field to determine whether or not the write registers were initialized at power on. EepromStatus Read Register Field Definitions This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 53 IRMCK203 FOCDiagnosticDataSupplement Register Group (Read Registers) Byte Offset 7 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 SPARE 6 5 Bit Position 4 3 ElecAngR (LSBs) (R) 2 1 0 ElecAngR (MSBs) (R) SpdRef (LSBs) (R) SpdRef (MSBs) (R) SpdErr (LSBs) (R) SpdErr (MSBs) (R) IqRefR (LSBs) (R) IqRefR (MSBs) (R) FOCDiagnosticDataSupplement Read Register Map Field Name ElecAngR SpdRef SpdErr IqRefR Access Field Description (R/W) R Electrical angle. R Speed PI controller reference input. R Speed PI controller error. R Speed PI controller output. FOCDiagnosticDataSupplement Read Register Field Definitions TraceBufferStatus Register Group (Read Registers) The data registers in the TraceBufferStatus Register group access a single entry in the trace buffer. A read of the TrcDataA (LSBs) register causes the internal trace buffer pointer to increment to the next entry. To retrieve all data items for a single trace buffer entry, read the TrcDataA and TrcDataB registers as a single 32-bit access, or read the TrcDataA (LSBs) register last. See the description of the TraceBufferControl write register group for more information about using the trace function. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 54 IRMCK203 Byte Offset 7 0x1F 0x20 0x21 0x22 0x23 SPARE 6 TrcSt 5 Bit Position 4 3 2 SPARE 1 0 TrcDataA (LSBs) (R) TrcDataA (MSBs) (R) TrcDataB (LSBs) (R) TrcDataB (MSBs) (R) TraceBufferStatus Read Register Map Field Name TrcSt TrcDataA TrcDataB Access (R/W) R R R Field Description Trace data collection state. 0 = Idle, 1 = Armed/Collecting, 2 = Triggered, 3 = Done Collecting Data. Data "A" item from current trace buffer location. Data "B" item from current trace buffer location. TraceBufferStatus Read Register Field Definitions ProductIdentification Registers (Read Registers) Byte Offset 7 0x7C 0x7D 0x7E 0x7F 6 5 Bit Position 4 3 ProductID (R) RegMapVerID (R) RevCodeID (LSBs) (R) RevCodeID (MSBs) (R) 2 1 0 ProductIdentification Read Register Map This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 55 IRMCK203 Field Name ProductID RegMapVerID RevCodeID Access (R/W) R R R Field Description Product identification code. Current register map version code. IRMCK203 Revision Code. Revision code format is "XX.XX", where each "X" is a 4-bit hexadecimal number. ProductIdentification Read Register Field Definitions This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 56 IRMCK203 Appendix B Package This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 57 IRMCK203 IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105 Data and specifications subject to change without notice. 9/15/2003 http://www.irf.com Sales Offices, Agents and Distributors in Major Cities Throughout the World. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 58 |
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